1. Field of the Invention
This inventions relates generally to communication receiver circuitry and, more particularly, to a system and method for selectively equalizing the frequency response of received communications signals in an integrated circuit (IC) receiver.
2. Description of the Related Art
As high-speed random data travel through an air or transmission line medium on their way to a receiver circuit, the data can become distorted with respect to time. This distortion is due to the non-ideal response of the medium to the different frequencies of the data stream. Typically, higher frequency information suffers the worst degradation. Correcting this distortion can, therefore, be a critical function in the performance data recovery circuits (DRC). That is, optimal performing receiver circuits must be capable of correcting for the medium-induced frequency roll-off.
It is well known to design systems with the goal of making the gain response of the system transfer function flat across a critical range of frequencies, with a desired phase margin of 180 degrees (in the parlance of Bode plot analysis). However, such a transfer function is difficult to achieve. To counteract gain roll-off and phase shifting, the amplitude of the transfer function can be peaked at higher frequencies, and the slope of the phase change modified by using a resistor and capacitor pair (RC) of components to generate an additional so-called xe2x80x9czeroxe2x80x9d in the transfer function. Thus, a zero can be used to compensate for the degradation of the high frequency portions of an input signal. It is also known to design a resonant zero using passive circuits, or active circuits using a transistor or a differential pair of transistors.
A zero can also be added to the transfer function of a system to counteract higher frequency degradation in the transmission of a signal. The zero compensates by increasing the gain in the region of the zero frequency. However, the additional of a zero to the transfer function comes at the price of added group delay, which can also degrade received communications. Further, if the input is not degraded during transmission, the additional zero tends to accentuate high frequency components of the input signal at the expense of the low frequency components.
It would be advantageous if an equalization circuit at the input of a receiver IC could be engaged to compensate for amplitude and phase degradation in specific frequency ranges.
It would be advantageous if the above-mentioned equalization circuit could be selectably engaged.
It would be advantageous if a plurality of equalization sections could be engaged to compensate for different ranges of high frequency amplitude and phase degradation.
It would be advantageous if the above-mention plurality of equalization circuits could be selectively engaged to provide a plurality of selectable equalization ranges, or not engaged in situations where degradation is not present.
Accordingly, a selectably engagable equalization circuit is provided that functions by enabling one of two differential transistor pairs. The transistor pair that enables the frequency equalization function has a source degeneration impedance which is essentially one resistor in parallel with one capacitor. The parallel-connected RC network at the source results in a zero in the transfer function of the circuit. This zero is used to compensate for degraded phase. In addition, the magnitude response of the transfer function increases at frequencies above the zero frequency. Therefore, the circuit also compensates for amplitude degradation.
One unique feature of the circuit is that the transistor pair enabling the equalization function can be easily disabled, while a parallel non-equalizing transistor pair processes the input signal. Other circuitry features insure that the equalization transistor pair is completely off when the circuit is in the non-equalization mode, and that the source current for the equalization and non-equalization transistor pairs remains constant.
Additional details of the above-described selectable equalization circuit and a method for selectably equalizing an input signal to an IC receiver are described below.